The present invention relates to a circuit for compensating delay time of the digital signals transmitted through a transmission line between a signal driver and a receiver, and in particular, to such circuit connectable in parallel with the transmission line in order to reduce the delay time by advantageously modifying the edges of the signals.
Generally, a long transmission line between the signal driver and receiver develops resistive and capacitive impedance that deimpedes the output signal of a driver transmitted to a receiver, thus resulting in a flattened waveform of the signal with increased falling or rising times. Also, the resistive and capacitive impedance causes undesirable power consumption.
FIG. 1 shows a conventional circuit for solving the problem of increased resistive and capacitive impedance in a transmission line. A repeater RP is added between the signal driver 10 and receiver 20.
The repeater RP provided before receiver 20 corrects the distortion of the signal waveform caused by the resistance and capacitance of the transmission line, and reduces the time required for the rising or falling edge of the signal. The repeater generally includes a plurality of inverters connected in multiple stages. The number of the inverters should be even so that the phase of the input signal is the same as that of the output signal. Hence, a minimum of two inverters is necessary to cause delay of the signal. As a result, the repeater provides the correction of the signal waveform, but does not compensate the delay time of the signal.